ASIC Design /Verification Engineer

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どんな仕事かAIによる生成

最新のSoC向けHBMコントローラIPのRTL設計・実装を担当します。仕様書をもとにマイクロアーキテクチャを設計し、検証計画やテストベンチの構築、設計レビュー、グローバルチームとの連携を行います。若手エンジニアの指導や進捗・検証レポートの作成も担当します。

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RTL設計やマイクロアーキテクチャ設計の経験
UVM/VMM/OVMなどの検証手法やSystemVerilogの知識
SoC/ASIC設計フローや検証計画、カバレッジ重視の検証経験
シミュレーションツール、Unix環境、スクリプト言語（Perl, Python, TCL）
DDR、PCIE、AXI/CHI、SD/eMMC、Ethernet、USB、MIPIなどのプロトコル知識
英語でのコミュニケーション能力
BSEE（9年以上）またはMSEE（7年以上）の実務経験
Extensive hands-on experience with RTL design and micro-architecture development from functional specifications.
Proficiency in verification methodologies (UVM/VMM/OVM), SystemVerilog, and object-oriented verification techniques.
Deep understanding of SoC/ASIC design flows, verification planning, and coverage-driven verification.
Experience with simulation tools, Unix operating environments, and scripting languages (Perl, Python, TCL).
Solid knowledge of protocols such as DDR, PCIE, AMBA (AXI/CHI), SD/eMMC, Ethernet, USB, and MIPI.
Strong English communication skills and the ability to document and present technical concepts effectively.
BSEE with 9~10+ years or MSEE with 7~12+ years of relevant experience.

Advantageous: Experience with formal verification, firmware/embedded software, C/C++, and functional safety standards (ISO26262, FMEDA).

Innovative, self-motivated, and able to work independently with precision.
Exceptional problem-solving skills and keen attention to detail.
Effective communicator and active listener, adept at cross-functional collaboration.
Team-oriented and supportive, with a willingness to mentor and share knowledge.
Adaptable to new challenges, tools, and methodologies in a dynamic environment.
Committed to continuous learning and professional development.

職種: ハードウェアエンジニア
雇用形態: Employee
役職: Sr Staff若手エンジニアの指導
給与: 記載なし
勤務地: Tokyo, Tokyo, Japan
働き方: Remote Eligible No
学歴: 大学卒業以上
選考の流れ: When you apply to join us, your resume, skills, and experience are first reviewed for consideration.Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have.Next up is interviewing (in person or virtual).When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept!There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation.Once you’ve joined, your manager, team, and a peer buddy will help you get acclimated.
掲載日: 2026/10/24 15:26（1日前）
最終確認: 2026/10/25 02:09（今日）

Designing and implementing RTL-based HBM controller IP cores for cutting-edge SoC applications.
Interpreting and translating standard and product functional specifications into detailed micro-architectures.
Making architectural and methodological judgments for both design and verification activities.
Developing comprehensive verification strategies, including testbench architectures using SystemVerilog and UVM.
Creating and maintaining verification plans, item lists, coverage metrics, and checker definitions to ensure thorough validation.
Coordinating and leading design review meetings to ensure alignment and technical excellence across global teams.
Providing technical leadership and mentoring to junior engineers, setting quality standards and driving innovation.
Documenting progress, generating reports with “visible” verification metrics, and ensuring project milestones are met.

Delivering high-quality, robust HBM controller IP that accelerates time-to-market for Synopsys customers.
Enabling key innovations for AI, automotive, server, and data center applications through advanced memory interface solutions.
Reducing integration risk and enhancing system performance for a broad portfolio of end-customer products.
Driving technical excellence and best practices across global, cross-functional engineering teams.
Supporting Synopsys’ reputation as a leader in silicon IP by ensuring products meet and exceed industry standards.
Contributing to continuous improvement by identifying and implementing process, methodology, and tool enhancements.
Mentoring and developing the next generation of engineering talent within Synopsys.

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