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東京都のハードウェアエンジニアの求人84件応募資格・募集要項・仕事内容を見る
Optical Engine Chip Architecture and PHY Design Engineer for POI
- 勤務地
- 東京都中央区
- 休日
- 年間休日128日
- 雇用形態
- 正社員
- ハイブリッド勤務
- 在宅勤務あり
- フレックス
- 年間休日120日以上
- 退職金あり
- 住宅補助条件あり
- ※- Company-leased housing program (subject to eligibility criteria)
どんな仕事かAIによる生成
The role leads global technology strategy development across Photonics and Semiconductor fields, with expertise in Parallel Optical Interlink. It analyzes customer challenges, translates them into target specifications for material and process development, and drives development initiatives. The role also involves technical discussions in English with global partners and potential customers.
この求人に応募
応募資格
必須
- Experience with link budget calculations and modeling of link for simulation.
- Experience with analysis for degradation of optical link and research for compensation.
- Experience defining required performance on optical devices and components.
- Understanding modulation method and demodulation algorithm.
- Experience defining architecture for optical engines integrated with ASICs or SoCs.
- Understanding of co-packaged optics and chiplet-based designs for high-bandwidth interconnects.
- Deep knowledge of high-speed SerDes, PAM4 signaling, and optical PHY layer design.
- Familiarity with clock-data recovery (CDR), equalization, and link training for optical channels.
- Expertise in multi-lane optical interfaces (e.g., 400G/800G Ethernet, InfiniBand).
- Knowledge of optical modulation formats and encoding schemes.
- Experience with implementation model design.
- Experience prototyping for transmitter, receiver and link media and system performance evaluation.
- Experience with electrical-optical co-design for chip-to-optical engine integration.
- Understanding of thermal management and mechanical constraints for optical engines in advanced packaging (e.g., 2.5D/3D IC, silicon interposer).
- Experience with RF modeling in optical communication systems.
- Understanding RF degradation factor on link and devices.
- Proficiency in signal integrity (SI) and power integrity (PI) analysis for high-speed optical PHY.
- Familiarity with simulation tools: Cadence, Synopsys, Ansys HFSS, Lumerical for photonic modeling.
- Hands-on experience with optical PHY bring-up, BER testing, and compliance validation.
- Knowledge of IEEE and OIF standards for optical interconnects.
- Experience with requirement analysis for conformance on the technical standard.
- Ability to work across ASIC design, packaging, and optical component teams.
- Strong documentation and communication skills for architecture specs and design reviews.
- Familiarity with CPO (Co-Packaged Optics), PCIe, Ethernet, and InfiniBand standards.
- Awareness of roadmap trends in optical I/O for AI/HPC systems.
- Experience making contributions for standardization.
- Familiarity on the tool for architecture stage, and have breath knowledge on the tools for other design stages.
- Architecture: MATLAB/Simulink (system modeling), SystemVerilog/VHDL (RTL architecture)
- Circuit Design: Cadence Virtuoso, Synopsys Custom Compiler, Mentor Calibre (DRC/LVS)
- Simulation: Cadence Sigrity (SI/PI), Keysight ADS, Ansys HFSS, Lumerical, Zemax
- Verification: Cadence Xcelium, Synopsys VCS, IBIS-AMI models for compliance
- Testing & Validation: Lab instruments: Keysight Oscilloscopes, BERTs, Optical Power Meters, Components Analyzer, AWG
募集要項最終確認 10/16
- 職種
- ハードウェアエンジニア
- 雇用形態
- 正社員Full-time Employee
- 給与
- 700〜1200万円/年
- 給与の詳細
- 年収 700万円〜1,200万円 *Salary will be determined based on experience and skills. *The stated annual salary includes estimated overtime allowances and bonuses.
- 勤務地
- 1040031 東京都中央区京橋1-6-1三井住友海上テプコビル9F3230194 栃木県下野市下坪山17249850842 宮城県多賀城市桜木3-4-1
- 働き方
- Tokyo Office, Tochigi Headquarters, or Tagajo Site—depending on your preference, while utilizing hybrid work. The final work location will be discussed during the interview process.Remote Work Policy This position primarily follows a remote work style.We have introduced a remote work system to support diverse work styles and enhance productivity, allowing employees to work flexibly based on the nature of their duties and individual suitability.
- 勤務時間
- Working Hours: 9:00 – 17:45 Break: 45 minutes *In case of the Tokyo Office as the primary location. *Working conditions may vary depending on each location.Flexible Working Hours (Flextime System)Core Time: 10:00 AM – 2:45 PM *Working hours and core time may vary depending on the location.
- 年間休日
- 128日
- 休日・休暇
- - Two days off per week (Saturdays, Sundays, national holidays, and year-end/New Year holidays)- Paid leave: 17 to 24 days per year (granted from the date of employment)- Annual holidays: 128 days
- 福利厚生
- - Retirement benefit system- Company-leased housing program (subject to eligibility criteria)- Stock compensation plan (J-ESOP)- Benefit Station (employee benefits program)
- 社会保険
- - Health insurance- Workers’ compensation insurance- Employment insurance- Employees’ pension insurance
- 受動喫煙対策
- - No smoking allowed indoors
- 業務の変更の範囲
- All duties as determined by the company
- 掲載日
- 2026/07/03 21:14（106日前）
- 最終確認
- 2026/10/16 22:10（1日前）
仕事内容
Position Background
- To strengthen our technological capabilities in the Photonics domain, we are seeking a professional with expertise in Parallel Optical Interlink to lead global technology strategy development across Photonics and Semiconductor fields.
- You will analyze customer challenges, translate them into target specifications for material and process development, and drive development initiatives. The role also involves technical discussions in English with global partners and potential customers.
Optical Communication System Design
- Experience with link budget calculations and modeling of link for simulation.
- Experience with analysis for degradation of optical link and research for compensation.
- Experience defining required performance on optical devices and components.
- Understanding modulation method and demodulation algorithm.
Chip Architecture for Optical I/O
- Experience defining architecture for optical engines integrated with ASICs or SoCs.
- Understanding of co-packaged optics and chiplet-based designs for high-bandwidth interconnects.
PHY Design
- Deep knowledge of high-speed SerDes, PAM4 signaling, and optical PHY layer design.
- Familiarity with clock-data recovery (CDR), equalization, and link training for optical channels.
Parallel Optical Interconnect
- Expertise in multi-lane optical interfaces (e.g., 400G/800G Ethernet, InfiniBand).
- Knowledge of optical modulation formats and encoding schemes.
PoC for Novel Optical Network Architecture
- Experience with implementation model design.
- Experience prototyping for transmitter, receiver and link media and system performance evaluation.
Integration & Packaging
- Experience with electrical-optical co-design for chip-to-optical engine integration.
- Understanding of thermal management and mechanical constraints for optical engines in advanced packaging (e.g., 2.5D/3D IC, silicon interposer).
- Experience with RF modeling in optical communication systems.
- Understanding RF degradation factor on link and devices.
Modeling & Simulation
- Proficiency in signal integrity (SI) and power integrity (PI) analysis for high-speed optical PHY.
- Familiarity with simulation tools: Cadence, Synopsys, Ansys HFSS, Lumerical for photonic modeling.
Validation & Testing
- Hands-on experience with optical PHY bring-up, BER testing, and compliance validation.
- Knowledge of IEEE and OIF standards for optical interconnects.
- Experience with requirement analysis for conformance on the technical standard.
Collaboration
- Ability to work across ASIC design, packaging, and optical component teams.
- Strong documentation and communication skills for architecture specs and design reviews.
Industry & Standards
- Familiarity with CPO (Co-Packaged Optics), PCIe, Ethernet, and InfiniBand standards.
- Awareness of roadmap trends in optical I/O for AI/HPC systems.
- Experience making contributions for standardization.
PHY design tools
- Familiarity on the tool for architecture stage, and have breath knowledge on the tools for other design stages.
Design Stage and Tools
- Architecture: MATLAB/Simulink (system modeling), SystemVerilog/VHDL (RTL architecture)
- Circuit Design: Cadence Virtuoso, Synopsys Custom Compiler, Mentor Calibre (DRC/LVS)
- Simulation: Cadence Sigrity (SI/PI), Keysight ADS, Ansys HFSS, Lumerical, Zemax
- Verification: Cadence Xcelium, Synopsys VCS, IBIS-AMI models for compliance
- Testing & Validation: Lab instruments: Keysight Oscilloscopes, BERTs, Optical Power Meters, Components Analyzer, AWG
この求人は、デクセリアルズ株式会社の採用ページの内容をAIが読み取って整理したものです。応募の前に採用ページの原文を確かめてください。データの集め方企業サイト
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