Optical Engine Chip Architecture and PHY Design Engineer for POI

Job Description

1. 1Optical Communication System Design: link budget calculations, degradation analysis, defining required performance on optical devices, understanding modulation methods.
2. 2Chip Architecture for Optical I/O: defining architecture for optical engines integrated with ASICs or SoCs, understanding co-packaged optics and chiplet-based designs.
3. 3PHY Design: deep knowledge of high-speed SerDes, PAM4 signaling, optical PHY layer design, CDR, equalization, link training.
4. 4Parallel Optical Interconnect: expertise in multi-lane optical interfaces (400G/800G Ethernet, InfiniBand), knowledge of modulation formats and encoding schemes.
5. 5PoC for Novel Optical Network Architecture: implementation model design, prototyping for transmitter, receiver, link media, system performance evaluation.
6. 6Integration & Packaging: electrical-optical co-design, thermal management, mechanical constraints, RF modeling.
7. 7Modeling & Simulation: SI/PI analysis, simulation tools (Cadence, Synopsys, Ansys HFSS, Lumerical).
8. 8Validation & Testing: optical PHY bring-up, BER testing, compliance validation, knowledge of IEEE and OIF standards.
9. 9Collaboration: work across ASIC design, packaging, and optical component teams, documentation and communication skills.
10. 10Industry & Standards: familiarity with CPO, PCIe, Ethernet, InfiniBand standards, roadmap trends in optical I/O for AI/HPC systems.
11. 11Design Stage and Tools: architecture (MATLAB/Simulink, SystemVerilog/VHDL), circuit design (Cadence Virtuoso, Synopsys Custom Compiler, Mentor Calibre), simulation (Cadence Sigrity, Keysight ADS, Ansys HFSS, Lumerical, Zemax), verification (Cadence Xcelium, Synopsys VCS, IBIS-AMI), testing (Keysight Oscilloscopes, BERTs, Optical Power Meters, Components Analyzer, AWG).

Position Background

1. 1Seeking a professional with expertise in Parallel Optical Interlink to lead global technology strategy development across Photonics and Semiconductor fields.
2. 2Analyze customer challenges, translate them into target specifications for material and process development, and drive development initiatives.
3. 3Role involves technical discussions in English with global partners and potential customers.

応募資格（必須）

• Experience with link budget calculations and modeling of link for simulation.
• Experience with analysis for degradation of optical link and research for compensation.
• Experience defining required performance on optical devices and components.
• Understanding modulation method and demodulation algorithm.
• Experience defining architecture for optical engines integrated with ASICs or SoCs.
• Understanding of co-packaged optics and chiplet-based designs for high-bandwidth interconnects.
• Deep knowledge of high-speed SerDes, PAM4 signaling, and optical PHY layer design.
• Familiarity with clock-data recovery (CDR), equalization, and link training for optical channels.
• Expertise in multi-lane optical interfaces (e.g., 400G/800G Ethernet, InfiniBand).
• Knowledge of optical modulation formats and encoding schemes.
• Experience with implementation model design.
• Experience prototyping for transmitter, receiver and link media and system performance evaluation.
• Experience with electrical-optical co-design for chip-to-optical engine integration.
• Understanding of thermal management and mechanical constraints for optical engines in advanced packaging (e.g., 2.5D/3D IC, silicon interposer).
• Experience with RF modeling in optical communication systems.
• Understanding RF degradation factor on link and devices.
• Proficiency in signal integrity (SI) and power integrity (PI) analysis for high-speed optical PHY.
• Familiarity with simulation tools: Cadence, Synopsys, Ansys HFSS, Lumerical for photonic modeling.
• Hands-on experience with optical PHY bring-up, BER testing, and compliance validation.
• Knowledge of IEEE and OIF standards for optical interconnects.
• Experience with requirement analysis for conformance on the technical standard.
• Ability to work across ASIC design, packaging, and optical component teams.
• Strong documentation and communication skills for architecture specs and design reviews.
• Familiarity with CPO (Co-Packaged Optics), PCIe, Ethernet, and InfiniBand standards.
• Awareness of roadmap trends in optical I/O for AI/HPC systems.
• Experience making contributions for standardization.
• Familiarity on the tool for architecture stage, and have breath knowledge on the tools for other design stages.
• Architecture: MATLAB/Simulink (system modeling), SystemVerilog/VHDL (RTL architecture)
• Circuit Design: Cadence Virtuoso, Synopsys Custom Compiler, Mentor Calibre (DRC/LVS)
• Simulation: Cadence Sigrity (SI/PI), Keysight ADS, Ansys HFSS, Lumerical, Zemax
• Verification: Cadence Xcelium, Synopsys VCS, IBIS-AMI models for compliance
• Testing & Validation: Lab instruments: Keysight Oscilloscopes, BERTs, Optical Power Meters, Components Analyzer, AWG

待遇・福利厚生

• Workers’ Compensation Insurance

求めるスキル・経験