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ハードウェアエンジニアの求人372件応募資格・募集要項・仕事内容を見る
Principal Engineer, Design
- 給与
- 記載なし
- 勤務地
- 記載なし
- 休日
- 記載なし
- 雇用形態
- 記載なし
どんな仕事かAIによる生成
Define, design and verify memory datapath blocks and close wave-pipelined and flop-to-flop timing paths. Design dataline sensing and array repair, develop semi-custom methodology, and work with layout on physical co-design. Champion AI adoption and technical leadership, including supporting silicon debug and mentoring engineers.
この求人に応募
応募資格
必須
- BS/MS in EE or related field with 8+ years in memory datapath, SRAM or high-speed custom design.
- Deep expertise in flop-to-flop and wave-pipelined timing closure (setup/hold, skew, min/max delay, PVT margin).
- Experience in sense amp, dataline or SRAM read/write design, including Monte Carlo/high-sigma verification.
- Proven collaboration with layout on floorplanning, extraction and post-layout timing correlation.
- Daily hands-on AI use, with concrete examples of AI-based workflows (prompts, scripts or agents) that improved productivity or design outcomes.
- NAND/DRAM/SRAM periphery experience: page buffer, column decoder, global data bus, or array-to-IO pipeline.
- Memory repair and redundancy design, and its impact on yield, area, timing and test time.
- Timing-adjustment techniques (delay trims, DLL/DCC, training) and aging effects (NBTI/HCI).
- Building AI agents, LLM/RAG pipelines or ML models for IC design, verification or debug.
- Advanced CMOS device physics, mismatch modeling (BSIM), and low-power techniques (clock/power gating, leakage).
- Working knowledge of STA and semi-custom flows mixing custom and standard-cell logic.
募集要項最終確認 10/28
- 職種
- ハードウェアエンジニア
- 雇用形態
- 記載なし
- 役職
- Principal Engineer
- 給与
- 記載なし
- 勤務地
- 記載なし
- 働き方
- 記載なし
- 経験年数
- 8年以上
- 学歴
- 大学院修了以上
- 掲載日
- 2026/10/28 16:16（1日前）
- 最終確認
- 2026/10/28 22:16（1日前）
仕事内容
Datapath architecture
- Define, design and verify internal datapath blocks (page buffer-to-IO data buses, wave pipelines, FIFOs, SER/DES front ends and datapath clocking) to meet bandwidth, timing and power targets.
Timing closure
- Architect and close wave-pipelined and flop-to-flop paths, including setup/hold, skew/jitter budgets, PVT delay tracking, and delay trims across PVT and aging.
Dataline sensing
- Design dataline sense amps and precharge/latch sensing, covering offset, Monte Carlo/high-sigma margin, coupling and IR drop.
募集内容
- Design column repair, fuse/repair storage and redundancy muxing with no bandwidth or timing penalty; verify all repair configurations with test, PE and FW.
AI-driven design
- Use AI daily for RTL generation, scripting, and timing/waveform analysis; make specs and checklists AI-consumable and build agents that automate timing, Monte Carlo and repair-coverage checks.
Semi-custom methodology
- Lead the move from SPICE-only closure to a semi-custom flow with characterized custom cells, SDC/STA sign-off, STA-to-SPICE correlation, and synthesis/APR/ECO flows.
Physical co-design
- Drive floorplan, bus routing and RC-aware delay matching with layout, and correlate post-layout timing.
募集内容
- Champion AI adoption and best practices, define interface specs with cross-functional teams, support silicon debug, and mentor engineers.
この求人は、マイクロンメモリジャパン株式会社の採用ページの内容をAIが読み取って整理したものです。応募の前に採用ページの原文を確かめてください。データの集め方企業サイト
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