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電気設計・回路設計の求人769件応募資格・募集要項・仕事内容を見る
Semiconductor Principal Design Engineer
- 給与
- 記載なし
- 勤務地
- 記載なし
- 休日
- 記載なし
- 雇用形態
- 記載なし
どんな仕事かAIによる生成
Designs and optimizes TSV interface circuits connecting memory and logic dies, as well as wide internal parallel data buses across arrays, channels and pseudo-channels. The role covers datapath architecture, timing, signal and power integrity, verification, DFT, and post-silicon validation. It also involves collaboration with process technology, packaging, assembly, and cross-functional teams.
この求人に応募
応募資格
必須
- BS or MS in Electrical Engineering with 8+ years of relevant experience in memory circuit design, preferably in DRAM, NAND or other high-density memory technologies.
- Experience with TSV(Through-Silicon Via) interface circuit design or high-speed memory interface design(NV-LPDDR4, DDR4/5, LPDDR5/6, HBM3/3E/4), including timing analysis, parasitic modeling, and signal integrity.
- Advanced knowledge and understanding of highly parallel bus performance, power and area optimization including clock distribution and skew management across wide data paths, and EpB(Energy per Bit) optimization in the context of 3D-stacked memory architectures.
- Experience managing complex circuit design projects spanning multiple functional blocks and cross-functional teams, with the ability to effectively communicate design trade-offs, schedule progress, and technical outcomes to both design and non-design stakeholders
- Applying AI to daily work and design work flow to improve quality and efficiency.
- Hands on experience in utilizing AI to improve quality of design and efficiency
- Experience on chip level PDN optimization
- Comprehensive understanding on CMOS device and device reliability
- Comprehensive understanding on CMOS BSIM model and CMOS target for high speed IO operation
- Experience with signal/power integrity, power delivery network design, physical design
募集要項最終確認 10/21
- 職種
- 電気設計・回路設計
- 雇用形態
- 記載なし
- 役職
- Principal Design Engineer
- 給与
- 記載なし
- 勤務地
- 記載なし
- 働き方
- 記載なし
- 経験年数
- 8年以上
- 学歴
- 大学卒業以上
- 掲載日
- 2026/10/12 05:15（10日前）
- 最終確認
- 2026/10/21 22:16（1日前）
仕事内容
募集内容
- Design and optimize TSV(Through-Silicon Via) interface circuits connecting memory die to logic die including Rx/Tx circuit for internal TSV channels, impedance matching and timing margin analysis.
- Develop and characterize TSV electrical models and define circuit design constraints for datapath interface.
- Define and implement signal integrity requirements for the TSV channel, including eye margin, crosstalk, and noise budget analysis
- Define and implement power integrity requirements using TSV for highly parallel IO and array operations
- Design and verify TSV-specific DFT (Design for Testability) circuits including loopback test modes, TSV continuity checks, and lane redundancy/remapping logic
- Interface with process technology and DTCO teams to optimize TSV design rules, standard cell usage, and layout strategies for the internal datapath
- Develop and execute functional verification plan for TSV interface and internal parallel bus including full chip circuit simulation and Verilog regression
- Design and optimize the wide internal parallel data bus spanning multiple arrays, channels and pseudo-channels, ensuring timing closure and signal integrity across the full parallel bus
- Architect the data path from the page buffer through data line sense amplifier, redundancy logic, and bus driver to the TSV output interface, managing parallelism across bank groups and banks.
- Develop clocking and synchronization strategies for the highly parallel internal bus including wave pipeline design, clock distribution, and skew management
- Implement and optimize column redundancy and lane repair schemes compatible with HBM like highly parallel bus architecture
- Define timing budgets and perform timing analysis across the full internal datapath under PVT variations
- Support post-silicon validation, debug and correlation activities; identify schematic edits and drive necessary tape-out revisions.
- Collaborate with packaging and assembly teams to ensure TSV reliability constraints are met within the datapath floorplan
- Communicate with project integration and other functional teams in design on specifications of major block interfaces
- Communicate with PE to drive silicon experiments and propose fixes and improvements for yield improvement and silicon debugging.
- Communicate with Apps regarding introduction of new specs and limitations based on design requirements and limitations.
- Document and review final results with experts and stakeholders
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応募はマイクロンメモリジャパン株式会社の採用ページで受け付けています。このページは採用ページの掲載内容をもとに構成しているため、最新の応募条件は募集元でご確認ください。