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Sr Engineer, Compiler
- 給与
- 記載なし
- 勤務地
- 記載なし
- 休日
- 記載なし
- 雇用形態
- 正社員
- オフィス出社
どんな仕事かAIによる生成
RenesasのHPCチームで、次世代自動車向けSoC上でAIワークロードを最適に実行するためのコンパイラおよびコード生成技術を推進します。AIコンパイラのアーキテクチャ設計、グラフ最適化、NPU向け性能最適化を担い、SoCおよびAIアクセラレータのアーキテクトと連携します。
この求人に応募
応募資格
必須
- MS/PhD (or equivalent experience) in Computer Science, EE, or related field
- Deep experience building AI compilers, accelerator backends, or graph optimization frameworks
- Strong expertise in graph optimization and performance optimization for NPUs or custom accelerators
- Experience with MLIR, LLVM, TVM‑like systems, or proprietary compiler IRs
- Excellent C/C++ and Python skills
- Solid understanding of AI inference workloads (CNNs, transformers, perception or generative models)
- Strong communication skills are required, e.g. agile development experience in Scrum team (Product Owner or Scrum Master)
歓迎
- Experience with automotive or safety‑critical systems
- Background in heterogeneous SoCs (CPU/GPU/DSP/NPU)
- Performance modeling or hardware–software co‑design experience
募集要項最終確認 10/22
- 職種
- システムエンジニア（SE・SIer）
- 雇用形態
- Full-time
- 役職
- Sr Engineer
- 給与
- 記載なし
- 勤務地
- 小平市
- 働き方
- 3. リモート No
- 福利厚生
- 私たちは、競争力のある報酬制度に加え、充実した福利厚生をご用意しています。福利厚生の詳細については、選考プロセスの中でご案内いたします。
- 学歴
- 大学院修了以上
- 掲載日
- 2026/09/18 20:51（34日前）
- 最終確認
- 2026/10/22 02:51（今日）
仕事内容
Job Description
- As an AI Compiler Engineer on the Renesas HPC team, you will be responsible for driving compiler and code generation technologies that unlock the full compute potential of Renesas next-generation automotive System-on-Chip platforms, including advanced 3 nm silicon for software-defined vehicles (SDVs). Your work will directly impact how AI workloads — from perception and sensor fusion to in-vehicle assistants and advanced driver assistance — are translated into highly optimized, safe, and power-efficient execution on Renesas hardware.
- This role bridges software compiler development, AI model lowering/optimization, and hardware-software co-design, enabling Renesas SoCs to deliver industry-competitive performance, efficiency, and functional safety required by multi-domain automotive applications..
- Lead AI compiler architecture across model ingestion, graph optimization, lowering, code generation, and runtime integration
- Design and implement graph‑level optimizations (operator fusion, quantization‑aware rewrites, memory‑aware scheduling, partitioning)
- Drive performance optimization for target NPUs, including tiling, tensor layout, and multi‑core execution strategies
- Partner with SoC and AI accelerator architects to influence hardware features through compiler insights
- Own performance KPIs for real automotive AI workloads using simulators, profilers, and silicon‑correlated models
- Ensure compiler outputs meet automotive requirements (real‑time behavior, determinism, quality expectations)
- Mentor senior engineers and set technical direction without people‑management responsibilities
Impact & Differentiators
- Renesas’ Gen5 R-Car automotive SoC lineup, including flagship 3 nm devices like the R-Car X5H, is among the first highly integrated multi-domain automotive SoCs built on advanced 3 nm process technology, designed to run ADAS, IVI, gateway, and next-gen SDV workloads on a centralized platform. These platforms deliver high AI performance (e.g., multi-hundreds of TOPS), scalable chiplet-based acceleration, and power efficiency tailored for electrified and autonomous vehicles while meeting stringent functional safety standards. An AI Compiler Engineer enables this hardware vision by ensuring that state-of-the-art AI models and computational kernels are efficiently mapped to the silicon fabric — directly enhancing performance, reducing latency and energy, and accelerating software adoption in automotive ecosystems where compute efficiency and safety are paramount.
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