どんな仕事かAIによる生成

Responsible for the architecture, design, integration, and implementation of advanced digital and mixed-signal ICs and SoCs. The role works with architecture, verification, DFT, physical design, firmware, and analog design teams across the product development lifecycle, from specification and architecture definition through silicon validation and production release.

応募資格・募集要項・仕事内容を見る

応募資格

必須

MSEE or Ph.D. in Electrical Engineering with 8+ years of relevant industry experience, or BSEE with 12+ years of relevant industry experience.
Strong background in digital IC and SoC architecture, design, and implementation.
Proven experience with SoC interconnects and protocols including AHB, APB, AXI, USB, I2C/I3C, SPI, and UART.
Strong knowledge of embedded memory architectures including SRAM, OTP, MTP, and Flash.
Extensive hands-on experience with RTL design using Verilog/SystemVerilog.
Experience with the complete ASIC/SoC development flow, including:
RTL design and simulation
SoC integration
Lint and design quality checks
CDC and RDC verification
Logic synthesis
DFT implementation
SDC constraint development
Static Timing Analysis (STA)
Timing closure and design signoff
Strong understanding of multi-clock designs, reset architecture, and low-power design methodologies.
Experience driving technical debug and resolution of functional, timing, and silicon issues.
Strong communication, problem-solving, and teamwork skills.
AI savvy and able to leverage AI tools to improve engineering productivity and design quality.

歓迎

Mixed-signal IC development experience and understanding of analog/digital integration challenges.
Experience with industry-standard EDA tools such as Synopsys Design Compiler, PrimeTime, SpyGlass, VC Static, Verdi, and Cadence design environments.
Hands-on experience integrating and debugging Arm® processor subsystems (Cortex-M0, Cortex-M0+, Cortex-M3, Cortex-M33, or similar Arm cores), including AHB/APB interconnects, memory subsystems, interrupt controllers, debug infrastructure, boot flows, and firmware interaction.
Experience with high-speed interface design and implementation.
Familiarity with FPGA prototyping and emulation flows.
Mandarin language proficiency is a plus due to collaboration with engineering teams in China.

求める人物像

Highly motivated self-starter with a passion for technical innovation.

募集要項最終確認 10/6

職種: ハードウェアエンジニア
雇用形態: Full-time
役職: Sr Staff
給与: 記載なし
勤務地: San Jose
働き方: リモート No
福利厚生: We believe in rewarding our employees with a competitive benefits package alongside their salary.
学歴: 大学卒業以上
掲載日: 2026/10/06 02:51（今日）
最終確認: 2026/10/06 02:51（今日）

仕事内容

Job Description

At Renesas, you will be part of a global engineering organization that values technical excellence, innovation, and collaboration. We offer opportunities to work on complex mixed-signal and digital SoC products with teams distributed across the United States and Asia, contributing to cutting-edge semiconductor solutions from concept to production.
We are seeking an experienced Sr Staff Digital Design Engineer to join the Analog & Connectivity Business Group. In this role, you will be responsible for the architecture, design, integration, and implementation of advanced digital and mixed-signal ICs and SoCs. The ideal candidate possesses strong expertise in digital design methodologies, RTL development, SoC integration, and design signoff, with a proven track record of delivering successful silicon products.
You will work closely with architecture, verification, DFT, physical design, firmware, and analog design teams throughout the product development lifecycle, from specification and architecture definition through silicon validation and production release.

Responsibilities

Define digital architecture and micro-architecture for complex mixed-signal and SoC products.
Develop high-quality RTL using Verilog/SystemVerilog and participate in design reviews.
Drive SoC and subsystem integration, including internal bus architectures and peripheral interfaces.
Develop and validate timing constraints, synthesis scripts, and implementation flows.
Analyze and resolve CDC, RDC, Lint, and timing issues to achieve design signoff.
Collaborate with verification teams on test planning, coverage closure, and debugging.
Support DFT implementation including scan, MBIST, JTAG, and production test methodologies.
Work with physical design teams to achieve power, performance, and area goals.
Perform silicon bring-up, debug, characterization, and root-cause analysis of silicon issues.
Create and maintain design documentation throughout the development cycle.
Contribute to technology and architecture definition for future product generations.

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Sr Staff Digital Engineer

どんな仕事かAIによる生成

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応募資格

必須

歓迎

求める人物像

募集要項最終確認 10/6

仕事内容

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Responsibilities

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