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Semiconductor Principal Design Engineer, Non‑Volatile Engineering Group
- 給与
- 記載なし
- 勤務地
- 記載なし
- 休日
- 記載なし
- 雇用形態
- 記載なし
どんな仕事かAIによる生成
Own internal NAND datapath circuit design, including redundancy circuits, wave-pipeline or pulse-based datapath architecture, and data line sensing circuits. Define scalable datapath architectures and timing schemes, lead layout-aware implementation and simulation, and drive silicon correlation, root-cause analysis, design reviews, and cross-functional communication.
この求人に応募
応募資格
必須
- BS or MS in Electrical Engineering with 8+ years of relevant experience
- Experience in physical design flows and optimization
- Proven ownership of blocks from concept -> design -> layout -> signoff -> silicon correlation, CMOS analog/mixed-signal circuit design and device physics fundamentals
- High-speed datapath timing analysis (including nontraditional timing such as wave-pipelined/pulse-based)
- Layout parasitics and physical implementation impact on circuit behavior
- Strong simulation and debug skills (SPICE/Fast-SPICE, corner/MC analysis, failure-mode thinking)
- Experience with managing complex design projects, effectively communicating progress and outcomes
- Direct experience in NAND datapath and/or DRAM datapath design.
- Wave-pipelining, self-timed, or pulse-latched pipeline design techniques
- Redundancy/repair architecture experience in dense arrays (including repair timing implications)
- Experience on DRAM interface(e.g. DDR4/5, LPDDR5/6, HBM3/3E/4) as well as other industry standard interfaces.
- Comprehensive understanding on CMOS device and device reliability
募集要項最終確認 10/21
- 職種
- ハードウェアエンジニア
- 雇用形態
- 記載なし
- 役職
- Principal Design Engineer
- 給与
- 記載なし
- 勤務地
- 記載なし
- 働き方
- 記載なし
- 経験年数
- 8年以上
- 学歴
- 大学卒業以上
- 掲載日
- 2026/10/12 05:15（10日前）
- 最終確認
- 2026/10/21 22:16（1日前）
仕事内容
募集内容
- Own internal NAND datapath circuits including array redundancy circuits, wave pipeline / pulse based datapath arctitechture and data line sensing circuits. Define scalable datapath architecture supporting multi-plane and high-parallelism operation. Define and analyse clock/data timing schemes for long interconnects and large-array topologies. Lead timing adjustment and skew management strategy. Drive layout-aware circuit design with attention to: matching/symmetry for sensing paths, shielding/guarding for sensitive nodes. Parasitic-aware sizing and RC-driven timing closure. Array pitch constraints, blockages and repeatable layout templates. Partner tightly with layout to review critical routes and implement practical fixes. Perform SPICE/Fast-SPICE simulations across PVT, aging and variability via Monte Carlo. Define characterization structures and debug plans to correlate silicon behavior vs. simulation. Drive root-cause analysis for margin/yield issues tied to datapath timing, redundancy paths or sensing robustness. Lead design reviews and unblock partners with clear technical decisions. Mentor other engineers; create reusable design collateral (checklists, templates, signoff methodology). Communicate tradeoffs effectively (PPA, margin, schedule, risk) and propose mitigation plans Communicate with project integration and other functional teams in design on specifications of major block interfaces
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