応募資格

必須

Bachelor's or Master's in Electrical Engineering or Computer Engineering with 5+ years of hands-on verification experience for IP cores or SoC designs (or Master's with 3+ years)
Strong SystemVerilog and HVL coding skills with proven ability to build testbenches, write constrained-random tests, and implement functional coverage
Direct experience with UVM, VMM, or OVM methodologies applied to real verification projects
Hands-on proficiency with industry-standard simulators such as VCS, NC (Xcelium), or MTI (Questa) and their associated debugging tools
Solid understanding of functional coverage and code coverage concepts, and how to use them to drive verification closure

歓迎

Experience with Verilog for reading and understanding RTL is highly desired
Familiarity with scripting languages like Perl or Python for automation and regression management is a strong plus

求める人物像

You can read a protocol specification, identify the verification-critical scenarios, and turn that into a test plan without someone walking you through it
When a regression fails, you do not wait for someone else to triage it, you pull the logs, check the waveforms, and narrow down the root cause
You communicate clearly with design engineers about bugs, coverage gaps, and quality risks without creating unnecessary friction or noise
You are self-driven enough to manage your own verification tasks, track your coverage metrics, and escalate when you are blocked, not after you are stuck
You can work across time zones with a global team, contribute to reviews, and share what you learn without needing constant oversight
You understand that verification is a team effort, you help others debug, review test plans, and contribute to shared infrastructure when it makes the team better

募集要項最終確認 10/6

職種: QAエンジニア
雇用形態: Employee
役職: Staff Engineer
給与: 記載なし
勤務地: Bengaluru, Karnataka, India
働き方: Remote Eligible No
休日・休暇: company holidaysETO and FTO ProgramsMaternity and paternity leave
福利厚生: Comprehensive medical and healthcare plans that work for you and your family.In addition to company holidays, we have ETO and FTO Programs.Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.Save for your future with our retirement plans that vary by region and country.Competitive salaries.
学歴: 大学院修了以上
選考の流れ: When you apply to join us, your resume, skills, and experience are first reviewed for consideration.Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have.Next up is interviewing (in person or virtual). You’ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you’re looking for in your next role.Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept!There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation.Once you’ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you’ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!
掲載日: 2026/10/05 20:10（1日前）
最終確認: 2026/10/06 02:10（今日）

仕事内容

What You'll Be Doing

Build and maintain UVM-based verification environments for DesignWare IP cores across USB, PCI Express, Ethernet, and AMBA protocols
Develop test plans by analyzing specifications, identifying coverage holes, and defining verification strategies at both unit and system levels
Write SystemVerilog testbenches, constrained-random tests, directed tests, and functional coverage models that drive quality metrics to closure
Debug RTL and testbench issues using VCS, NC, or MTI simulators, trace waveforms, and work with design engineers to resolve root causes
Manage regressions, analyze coverage reports, close functional and code coverage gaps, and drive IP to signoff quality
Collaborate with a global verification team, participate in reviews, and contribute to methodology improvements across the DesignWare IP portfolio
Integrate and work with Verification IP (VIP) for industry-standard protocols to accelerate environment bring-up and test development

The Impact You Will Have

Ensure DesignWare IP cores meet the quality and reliability standards that customers depend on for their SoC designs
Catch critical bugs before tapeout, reducing costly respins and protecting Synopsys reputation for silicon-proven IP
Drive coverage closure and verification signoff for IP that ships in high-volume applications across automotive, mobile, data center, and AI markets
Contribute verification methodology improvements that make the entire DesignWare team more efficient and effective
Enable faster time-to-market for customers by delivering thoroughly verified, reusable IP blocks
Influence design quality through early feedback, test plan reviews, and cross-functional collaboration with RTL and architecture teams
Help scale verification processes and environments that support one of the industry's broadest IP portfolios

The Team You'll Be Part Of

You will join the DesignWare IP Verification R&D team at the Bangalore Design Center, working as part of a global team of verification engineers responsible for ensuring the quality of Synopsys' industry-leading IP portfolio. The team verifies synthesizable cores across multiple high-speed interface and interconnect protocols including USB, PCI Express, Ethernet, and AMBA. You will collaborate closely with RTL design teams and contribute to verification environments and methodologies that support one of the broadest IP portfolios in the semiconductor industry.

この求人は、日本シノプシス合同会社の採用ページの内容をAIが読み取って整理したものです。応募の前に採用ページの原文を確かめてください。データの集め方企業サイト

ASIC Digital Design , Staff Engineer

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応募資格

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歓迎

求める人物像

募集要項最終確認 10/6

仕事内容

What You'll Be Doing

The Impact You Will Have

The Team You'll Be Part Of

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