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Staff Product Engineer - Physical Verification
給与
記載なし※ 募集要項に金額の記載がありません
- 勤務地
- 記載なし
- 雇用形態
- 記載なし
- 働き方
- オフィス出社
- 年間休日
- 記載なし
要約求人票をもとにAIがまとめたものです
Review customer and foundry specifications to develop, enhance, and maintain ICV rule decks and methodologies for physical verification requirements. Serve as the primary technical interface between customers, foundries, R&D, and product engineering teams, and lead project planning and execution to meet customer tapeout milestones. Drive improvements in tools and verification methodologies through automation, and provide technical leadership and customer training.
応募資格
必須
- BSc in Electrical Engineering or equivalent with at least 9 years of relevant experience, or MSc with at least 7 years of experience
- Thorough understanding of physical verification and hands-on experience with at least one physical verification tool like ICV, Calibre, PVS (Pegasus), or other ESD tools
- Extensive knowledge and hands-on experience in runset development for DRC, LVS, PERC, or ESD across multiple process nodes
- Excellent proficiency in Python, Perl, Shell, or TCL scripting language for automation and verification flow development
- Understanding of customer requirements from a physical design perspective, including layout, timing closure, and signoff constraints
- Hands-on experience with software development processes including project planning, version control systems like Git, and bug tracking tools
- Excellent teamwork and communication skills, with the ability to work effectively across global teams and time zones
求める人物像
- You can take a 200-page foundry design rule manual, a customer's failing layout, and a tight deadline, and deliver a working solution without losing your mind or the details
- You are comfortable explaining a complex LVS mismatch to a customer's layout team in terms they understand, and then turning around and filing a precise bug report for R&D with reproducible steps
- You manage multiple customer projects simultaneously without dropping threads, mixing up runset versions, or missing a tapeout milestone
- When a new EDA feature ships, you do not wait for documentation. You test it, break it, figure out where it fits, and decide whether it is ready for customer deployment
- You push back when a project plan does not account for foundry spec changes, tool limitations, or the reality of how long verification actually takes
- You see automation as a necessity, not a nice-to-have. If you are doing something manually more than twice, you script it
募集要項最終確認 10/2
- 職種
- テック
- 雇用形態
- Employee
- 役職
- Staff Product Engineer
- 給与
- 記載なし
- 勤務地
- Yongin-si, Gyeonggi-do, South Korea
- 働き方
- Remote Eligible No
- 学歴
- 大学卒業以上
- 掲載日
- 2026/10/02 14:38(今日)
- 最終確認
- 2026/10/02 14:38(今日)
仕事内容
What You'll Be Doing
- Review customer and foundry specifications to develop, enhance, and maintain ICV rule decks and methodologies for DRC, LVS, PERC, ESD, and other physical verification requirements
- Serve as the primary technical interface between customers, foundries, R&D, and product engineering teams to translate requirements, drive feature implementation, and resolve complex verification issues
- Lead project planning and execution by aligning resources, schedules, risks, and deliverables to achieve high-quality releases and meet customer tapeout milestones on time
- Drive continuous improvement of tools, runsets, and verification methodologies through automation, scripting in Python, TCL, Perl, or Shell, and scalable development frameworks
- Provide technical leadership by making architectural decisions, proposing solutions for advanced node and 3DIC challenges, conducting technical reviews, and mentoring team members
- Conduct technical presentations, workshops, training sessions, and product demonstrations to promote best practices and advanced verification methodologies to customers and foundries
- Collaborate across Synopsys product teams to evaluate, validate, and deploy new ICV features that enhance runset quality, improve productivity, and ensure interoperability across the signoff ecosystem
The Impact You Will Have
- Enable successful customer tapeouts by delivering high-quality physical verification solutions and signoff methodologies that actually work under real-world design constraints
- Accelerate customer productivity through optimized verification flows, automation, and scalable runset development practices that reduce turnaround time
- Strengthen customer and foundry partnerships through technical leadership, responsive support, and trusted execution that makes you the go-to engineer when things get hard
- Drive adoption and expansion of Synopsys physical verification technologies across advanced node, 3DIC, HBM, ESD solutions, and emerging semiconductor designs
- Influence product direction and future innovations through customer feedback, technology assessments, and cross-functional collaboration with R&D and product management
- Improve quality, scalability, and release predictability by establishing robust development processes and driving strategic enhancements across products and methodologies
The Team You'll Be Part Of
- You will join a dynamic Product Engineering team based in South Korea, dedicated to supporting leading semiconductor companies in their design and verification processes. The team collaborates closely with R&D, product management, and sales, ensuring customers receive the highest level of technical support and guidance. Together, you will play a crucial role in advancing Synopsys' technology adoption and driving customer success in a rapidly evolving industry.
Onboarding
- There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation.
Welcome!
- Once you’ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you’ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!
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